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HT82J97E
USB Joystick Encoder 8-Bit OTP MCU
Features
* Flexible total solution for applications that combine * Two 8-bit indirect addressing registers * One 16-bit programmable timer counter with over-
PS/2 and low-speed USB interface, such as mice, joysticks, and many others
* USB Specification Compliance - Conforms to USB specification V1.1 - Conforms to USB HID specification V1.1 * Supports 1 Low-speed USB control endpoint and 1
flow interrupt (shared with PA7, vector 0CH)
* One USB interrupt input (vector 04H) * HALT function and wake-up feature reduce power
consumption
* PA0~PA7 support wake-up function * Internal Power-On reset (POR) * Watchdog Timer (WDT) * 20 I/O ports (including 2-PWM output, PC2, PC3) * 2 PWM output (PC2, PC3) * Can produce PWM frequency range from 23Hz to
interrupt endpoint
* Each endpoint has 88 bytes FIFO * Integrated USB transceiver * 3.3V regulator output * External 6MHz or 12MHz ceramic resonator or crys-
tal
* 8-bit RISC microcontroller, with 2K14 EPROM
23kHz
* Built-in 8-bit Analog-to-Digital Converter, (6-channel
(000H~7FFH)
* 96 bytes RAM (20H~7FH) * 6MHz/12MHz internal CPU clock * 4-level stacks
for internal mode (PB0~PB5), 6-channel for external mode with VHL (PB7) and VRL (PB6))
* 20/28-pin SOP package
General Description
The USB MCU OTP body is suitable for USB mouse and USB joystick devices. It consists of a Holtek high performance 8-bit MCU core for control unit, built-in USB SIE, 2K14 EPROM and 96 bytes data RAM.
Block Diagram
U S B D + /C L K U S B D -/D A T A V33O U S B 1 .1 PS2 BP In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C M U X fS /4 P A 7 /T M R
TM R0 TM R0C
YS
E N /D IS W DTS In s tr u c tio n R e g is te r MP M U X DATA M e m o ry W D T P r e s c a le r WDT M U X S Y S C L K /4 W DT OSC
PAC In s tr u c tio n D ecoder ALU S h ifte r MUX PA
PORT A
PA0~PA6 P A 7 /T M R
PBC T im in g G e n e ra to r STATUS PB A /D PCC PC ACC PW M
PORT B
P B 0 /A N 0 ~ P B 5 /A N 5 P B 6 /V R L P B 7 /V R H
C o n v e rte r PORT C PC 0~PC 1 P C 2 /P W M 1 P C 3 /P W M 2
OSC2
OS R V V
C1 ES DD SS
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Pin Assignment
VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V33O U S B D + /C L K U S B D -/D A T A VSS V33O U S B D + /C L K U S B D -/D A T A RES PA0 PA1 PB2 PB3 PB4 9 10 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 OSCI OSCO VDD PA7 PA6 PA5 PA4 PA3 PA2 PB7 RES PA0 PA1 PC0 PC1 P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 P B 4 /A N 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OSCI OSCO VDD P C 3 /P W M 2 P C 2 /P W M 1 PA7 PA6 PA5 PA4 PA3 PA2 P B 7 /V R H P B 6 /V R L P B 5 /A N 5
H T82J97E 2 0 S O P -A
H T82J97E 2 8 S O P -A
Pin Description
Pin Name I/O ROM Code Option Description
PA0~PA7
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is conPull-low trolled by PAC (PA control register). Pull-high Pull-high resistor options: PA0~PA7 I/O Wake-up Pull-low resistor options: PA0~PA3 CMOS/NMOS/PMOS CMOS/NMOS/PMOS options: PA0~PA7 Wake-up options: PA0~PA7 Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB can be used as analog input of the analog to digital converter (determined by options). Pull-low resistor for options: PB2, PB3 Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB can be used as analog input of the analog to digital converter (determined by options). Wake-up options: PB4, PB7 Negative power supply, ground Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). PC2 can be used as PWM1 output PC3 can be used as PWM2 output Schmitt trigger reset input. Active low. Positive power supply 3.3V regulator output USBD+ or PS2 CLK I/O line USB or PS2 function is controlled by software control register USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock.
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB5/AN5 PB6/VRL
I/O
Pull-high Analog input
PB4/AN4 PB7/VRH
I/O
Pull-high Analog input Wake-up 3/4
VSS
3/4
PC0~PC3
I/O
Pull-high
RES VDD V33O USBD+/CLK USBD-/DATA OSCI OSCO
I 3/4 O I/O I/O I O
3/4 3/4 3/4 3/4 3/4 3/4
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Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTB VIL1 VIH1 VIL2 VIH2 IOL IOH RPD RPH1 RPH2 VLVR Parameter Operating Voltage Operating Current (6MHz Crystal) Standby Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Test Conditions VDD 3/4 5V 5V 5V 5V 5V 5V VOL=0.4V VOL=3.4V 3/4 3/4 3/4 3/4 Conditions 3/4 No load, fSYS=6MHz No load, system HALT 3/4 3/4 3/4 3/4 Min. 4 3/4 3/4 0 2 0 0.9VDD 2 -2.5 10 2 30 2.4 Typ. 3/4 7 300 3/4 3/4 3/4 3/4 4 -4 30 4.7 50 2.7 Max. 5.5 9 500 0.8 5
Ta=25C Unit V mA mA V V V V mA mA kW kW kW V
0.4VDD VDD 3/4 3/4 50 6 70 3
Output Sink Current for Other Ports 5V PA0~PA7, PB0~PB7 and PC0~PC3 Output Port Source Current 5V
Pull-down Resistance for PA0~PA3, PB2 5V and PB3 Pull-high Resistance for CLK and DATA 3/4
Pull-high Resistance for PA0~PA7, 3/4 PB0~PB7 and PC0~PC3 Low Voltage Reset 5V
A.C. Characteristics
Symbol fSYS fRCSYS tWDT tRF tSST tOSC fPWM Parameter System Clock (Crystal OSC) RC Clock with 8-bit Prescaler Register Watchdog Time-out Period (System Clock) USBD+, USBD- Rising & falling Time System Start-up Timer Period Crystal Setup PWM Cycle Frequency Test Conditions VDD 5V 5V 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 Min. 6 0 Typ. 3/4 32 3/4 3/4 1024 5 3/4 Max. 12 3/4 3/4 300 3/4 10 2300
Ta=25C Unit MHz kHz tRCSYS ns tSYS ms Hz
Without WDT prescaler 1024 3/4 Wake-up from HALT 3/4 6MHz or 12MHz 75 3/4 3/4 23
Note: Power-on period=tWDT+tSST+tOSC WDT Time-out in normal mode=1/fRCSYS256WDTS+tWDT WDT Time-out in HALT mode=1/fRCSYS256WDTS+tSST+tOSC
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Functional Description
Execution Flow The system clock for the microcontroller is derived from either 6MHz or 12MHz crystal oscillator, which used a frequency that is determined by the SCLKSEL bit of the SCC Register. The default system frequency is 12MHz. The system clock is internally divided into four nonoverlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory.
T1 T2 T3 T4 T1 T2
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *10 0 0 0 *9 0 0 0 *8 0 0 0 *7 0 0 0 *6 0 0 0 *5 0 0 0 PC+2 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *4 0 0 0 *3 0 0 1 *2 0 1 1 *1 0 0 0 *0 0 0 0
Mode Initial Reset USB Interrupt Timer/Event Counter Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits
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Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204814 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
ROM data by two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows:
The instructions TABRDC [m] (the current page, one page=256words), where the table locations is defined by TBLP (07H) in the current page. And the ROM code option TBHP is disabled (default). The instructions TABRDC [m], where the table locations is defined by registers TBLP (07H) and TBHP (01FH). And the ROM code option TBHP is enabled. The instructions TABRDL [m], where the table locations is defined by Registers TBLP (07H) in the last page (0700H~07FFH).
This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 00CH
This location is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Table location
Any location in the program memory can be used as look-up tables. There are three method to read the
000H 004H 00CH D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 W o r d s )
n00H nFFH
7FFH
L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 4 B its N o te : n ra n g e s fro m 0 to 7
Program Memory
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the OTP option TBHP is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Otherwise, the ROM code option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. Table Location
Instruction TABRDC [m] TABRDL [m]
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *10~*0: Table location bits @7~@0: TBLP bits P10~P8: Current program counter bits when TBHP is disabled TBHP register bit2~bit0 when TBHP is enabled
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Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). Data Memory - RAM for Bank 0 The data memory is designed with 968 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (968). Most are read/write, but some are read only. The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register (BP, 04H), PWM1 duty register (0DH), PWM2 duty register(0EH), Timer/Event Counter higher order byte register (TMRH;0FH), Timer/Event Counter lower order byte register (TMRL;10H), Timer/Event Counter control register (TMRC;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointers (TBLP;07H, TBHP;1FH), table higher-order b y t e r egi s t er ( TB LH ; 08H ) , s t at us r e g i st e r (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H), PWM Base Period Register (18H), I/O control registers (PAC;13H, PBC;15H, PCC;17H). USB/PS2 status and control register (USC;1AH), USB endpoint interrupt status register (USR;1BH), system clock control register (SCC;1CH). A/D converter status and control register (ADSC;1DH) and A/D converter result register (ADR;1EH). The remaining space before the 20H is reserved for future ex00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H USC USR SCC ADSC ADR TBHP PW M TM RH TM RL TM RC PA PAC PB PBC PC PCC B a s e P e r io d R e g is te r ( P D ) Bank 0 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C P W M 1 D u ty R e g is te r P W M 2 D u ty R e g is te r
G e n e ra l P u rp o s e DATA M EM ORY (9 6 B y te s ) 7FH
Bank 0 RAM Mapping panded usage and reading these locations will get 00H. The general purpose data memory, addressed from 20H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1).
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Data Memory - RAM for Bank 1 The special function registers used in the USB interface are located in RAM Bank1. In order to access Bank1 register, only the Indirect addressing pointer MP1 can be used and the Bank register BP should be set to 1. The RAM bank 1 mapping is as shown.
Bank 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 41H 42H 43H 44H 45H 46H 47H 48H 49H USC USR SCC ADSC ADR TBHP P ip e _ c tr l AW R STALL P IP E S IE S M IS C F IF O F IF O 1 0 PW M TM RH TM RL TM RC PA PAC PB PBC PC PCC B a s e P e r io d R e g is te r ( P D ) In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C P W M 1 D u ty R e g is te r P W M 2 D u ty R e g is te r
Indirect Addressing Register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) indirectly will return the result 00H. Writing indirectly results in no operation. The indirect addressing pointer (MP0) always points to Bank0 RAM addresses no matter the value of Bank Register (BP). The indirect addressing pointer (MP1) can access Bank0 or Bank1 RAM data according to the value of BP which is set to 0 or 1 respectively. The memory pointer registers (MP0 and MP1) are 8-bit registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended.
RAM Bank 1 Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers
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Labels C Bits 0 Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 Status Register The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the USB interrupt (1=enable; 0= disable) Unused bit, read as 0 Controls the Timer/Event Counter interrupt (1=enable; 0=disable) USB interrupt request flag (1=active; 0=inactive) Unused bit, read as 0 Internal timer/event counter request flag (1:active; 0:inactive) Unused bit, read as 0 INTC Register
AC Z OV PDF TO 3/4 3/4
1 2 3 4 5 6 7
Register
Bit No. 0 1 2
Label EMI EUI 3/4 ETI USBF 3/4 TF 3/4
INTC (0BH)
3 4 5 6 7
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The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC) will be set.
* Access of the corresponding USB FIFO from PC * suspend signal from PC * resume signal from PC * USB Reset signal
enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EUI and ETI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, USBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There is an oscillator circuit in the microcontroller.
OSC1
When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82J97E, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT82J97E receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82J97E is set and a USB interrupt is also triggered. When the HT82J97E receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82J97E is set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB interrupt is triggered and URST_Flag bit of the USC register is set. When the interrupt has been served, the bit should be cleared by firmware. The internal timer/even counter interrupt is initialized by setting the timer/event counter interrupt request flag (;bit 6 of the INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b Interrupt Source USB interrupt Timer/Event Counter overflow Priority Vector 1 2 04H 0CH
OSC2 C r y s ta l O s c illa to r
System Oscillator This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an external signal to conserve power. A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The HT82J97E can operate in 6MHz or 12MHz system clocks. In order to make sure that the USB SIE functions properly, user should correctly configure the SCLKSEL bit of the SCC Register. The default system clock is 12MHz. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of approximately 31ms. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determine by ROM code option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is dis-
The timer/event counter interrupt request flag (TF), USB interrupt request flag (USBF), enable timer/event counter interrupt bit (ETI), enable USB interrupt bit (EUI) and Rev. 1.30 9
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S y s te m C lo c k /4
W DT OSC ROM Code O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer abled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 31ms/5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5V. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can only be set to 10000 (WDTS.7~WDTS.3). If the device operates in a noisy environment, using the on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS Register The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset and only the PC and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the ROM code option - CLR WDT times selecRev. 1.30 10 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 tion option. If the CLR WDT is selected (i.e. CLRWDT times is equal to one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT and CLR WDT are chosen (i.e. CLRWDT times is equal to two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected). * The contents of the on-chip RAM and registers remain unchanged.
* The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports remain in their original status.
* The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
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wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are four ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * USB reset
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
V
DD
RES
Reset Circuit
HALT W DT
RES W a rm R eset
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration The functional unit chip reset status are shown below. PC Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay.
Timer/event Counter Off Input/output Ports Stack Pointer Input mode Points to the top of the stack
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The registers status are summarized in the following table. Reset (Power On) xxxx xxxx xxxx xxxx 00-0 1--000H 1xxx xxxx 1xxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RES Reset (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx RES Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx WDT Time-Out (HALT)* uuuu uuuu uuuu uuuu uu-u u--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB-Reset (Normal) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1100 0u00 u1uu 0000 uu00 u000 1000 0000 xxxx xxxx USB-Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1100 0u00 u1uu 0000 uu00 u000 1000 0000 xxxx xxxx
Register
TMRH TMRL TMRC Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC WDTS PA PAC PB PBC PC PCC PD AWR PIPE STALL SIES MISC FIFO0 FIFO1 USC USR SCC ADSC ADR
Note: * stands for warm reset u stands for unchanged x stands for unknown
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Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains a 16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by 4. Using the internal clock source, there is only 1 reference time-base for the timer/event counter. The internal clock source is coming from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths. There are 3 registers related to the timer/event counter; TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMRH will transfer the specified data and the contents of the lower-order byte buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload register is changed by each writing TMRH operations. Reading TMRH will latch the contents of TMRH and TMRL counters to the destination and the lower-order byte buffer, respectively. Reading the TMRL will read the contents of the lower-order byte buffer. The TMRC is the timer/event counter control register, which defines the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, Label (TMRC) 3/4 TE TON 3/4 TM0 TM1 Bits 0~2 3 4 5 Unused bit, read as 0 Defines the TMR active edge of the timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable the timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC Register which means that the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fSYS/4 (Timer). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fSYS/4. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 6 of the INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON Function
6 7
D a ta B u s fS
Y S /4
TM R TE TM 1 TM 0 TON
TM 1 TM 0
1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r
L o w B y te B u ffe r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R H /T M R L )
O v e r flo w to In te rru p t
Timer/Event Counter
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bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET can disable the corresponding interrupt services. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs (a timer/event counter reloading will occur at the same time). When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may result in a counting error, this must be taken into consideration by the programmer. Input/Output Ports There are 20 bidirectional input/output lines in the microcontroller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H] and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high/low resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS/NMOS/PMOS configurations can be selected (NMOS and PMOS are available for PA only). These control registers are mapped to locations 13H, 15H and 17H. After a chip reset, these input/output lines remain at high levels or in a floating state (depending on the pull-high/low options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H or 16H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. There are pull-high/low (PA only) options available for I/O lines. Once the pull-high/low option of an I/O line is selected, the I/O line have pull-high/low resistor. Otherwise, the pull-high/low resistor is absent. It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state.
V C o n tr o l B it
DD
D a ta B u s
D
PH
Q CK QB S PA PB PB PC 0~ 0 /A 6 /V 0~ PA N R PC 6 , P A 7 /T M R 0 ~ P B 5 /A N 5 L , P B 7 /V R H 3
W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK QB S PL M U X P A W a k e - u p O p tio n
W r ite D a ta R e g is te r
P o rt O u tp u t C o n fig u r a tio n R e a d D a ta R e g is te r P A W a k e -u p P A 7 /T M R AN 0~AN 5,VR L,VR H
Input/Output Ports Note: The outputs of PC2 and PC3 will be PWM outputs when PWM outputs are enabled.
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Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within the range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* For a valid LVR signal, a low voltage (0.9V~VLVR) must
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 2 .7 V 2 .4 V
LVR
exist for more than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses the OR function with the external
RES signal to perform a chip reset.
0 .9 V Note: VOPR is the voltage range for proper chip operation at 6MHz or 12MHz system clock.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.
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USB with MCU Interface
There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, Stall, Pipe, SIES, Misc, FIFO 0 and FIFO 1 in this buffer function. Register Name Pipe_ctrl Addr.+Remote Mem. Addr. Reserved Addr. 41H 42H Stall 43H Pipe 44H SIES 45H Misc 46H FIFO 0 48H FIFO 1 49H
Bank 1, Address 40H, 4AH, 4FH Register Memory Mapping
Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is 00000000 from MSB to LSB. Register Address 01000010B R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remote Wake-up Function 0: Not this function 1: The function exists
R/W
Address value Default value=00000000 Address+Remote_WakeUp Register
The PIPE_ctrl, STALL and PIPE are bitmap ones. The Pipe_ctrl Register is used for configuring IN (Bit=1) or OUT (Bit=0) Pipe. The default is defined as IN Pipe. The Pipe register represents whether the corresponding endpoint is accessed by host or not. After a USB interrupt signal is being sent out, the MCU can check which endpoint had been accessed. This register is set only after the host accessed the corresponding endpoint. The Stall register shows whether the corresponding endpoint works or not. As soon as the endpoint works improperly, the corresponding bit must be set. The bitmaps are listed as follows: Register Name Pipe_ctrl Stall Pipe R/W R/W R/W R Register Address 01000001B 01000011B 01000100B Bit7~Bit2 Reserved 3/4 3/4 3/4 Stall and Pipe Registers The SIES Register is used to indicate the present signal state which the USB SIE received and also determines whether the USB SIE has to change the device address automatically. Bit No. 7 6 5 4 3 2 1 0 Function MNI EOT CRC_ERR NAK IN OUT F0_ERR Adr_set Read/Write R/W R R/W R 01000101B R R/W R/W R/W SIES Registers Table Register Address Bit 1 Pipe 1 Pipe 1 Pipe 1 Bit 0 Pipe 0 Pipe 0 Pipe 0 Default Value 00000011 00000000 00000000
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Function Name Read/Write Description This bit is used to configure the USB SIE to automatically change the device address with the value of the Address+Remote_WakeUp Register (42H). When this bit is set to 1 by F/W, the USB SIE will update the device address with the value of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read the data from the device by the IN operation. The USB SIE will clear the bit after updating the device address. Otherwise, when this bit is cleared to 0, the USB SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp Register (42H). This bit is used to indicate when there are some errors that occurred when the FIFO0 is accessed. This bit is set by the USB SIE and cleared by F/W. This bit is used to indicate that there are OUT token (except for the OUT zero) that has been received. The F/W clears the bit after the OUT data has been read. Also, this bit will be cleared by the USB SIE after the next valid SETUP token is received. This bit is used to indicate that the current USB receiving signal from the PC Host is IN token. This bit is used to indicate that the USB SIE has transmitted the NAK signal to the Host in response to the PC Host IN or OUT token. This bit indicates that there are CRC error (bit=1). The programmer must do something to save the device and keep it alive. This bit is set by the USB SIE and cleared by F/W. End of transient flag, normal status is 1. If suspend=1 line & EOT=0 indicates that something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. This bit is for masking the NAK interrupt when MNI=1, the default value=0 SIES Function Table The Misc register is actually a command + status to control the desired FIFO action and to show the status of the desired FIFO. Every bits meaning and usage are listed as follows: Bit No. 7 6 5 4 3 2 1 0 Function Len0 Ready Set CMD Sel_pipe1 Sel_pipe0 Clear Tx Request Read/Write R/W R R/W R/W 01000110B R/W R/W R/W R/W Misc Registers Table Register Address
Adr_set
R/W
F0_Err
R/W
Out
R/W
IN NAK
R R
CRC_err
R/W
EOT MNI
R R/W
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Function Name Request Read/Write R/W Description After setting the other desired status, FIFO can be requested by setting this bit high active. After work has been done, this bit must be set low. Represents the direction and transition end of the MCU accesses. When being set as logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to logic 0 before terminating the request to represent a transition end. For reading action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1 after work is done. Represents MCU clear requested FIFO, even if FIFO is not ready. Determines which FIFO is desired, 00 for FIFO 0, 01 for FIFO 1 Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So, even if the MCU is busy, nothing is missed by the SETUP command from the host. Indicates that the desired FIFO is ready to work. Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after the next valid SETUP token is received. Misc Function Table The HT82J97E has two 88 bidirectional FIFO for the two endpoints (control and Interrupt). User can easily read/write the FIFO data by accessing the corresponding FIFO pointer register (FIFO0, FIFO1). The following are two examples for reading and writing the FIFO data: HT82J97E FIFO is read by packet. To read from FIFO, the following should be followed:
* Select one set of FIFO, set in the read mode (MISC
Tx
R/W
Clear Sel_pipe1 Sel_pipe0 Set CMD Ready Len0
R/W R/W R/W R R/W
HT82J97E allows a maximum of 8 bytes of data in each packet. The HT82J97E FIFO is written by packet. To write to FIFO, the following should be followed:
* Select a set of FIFO, set in the write mode (MISC TX
bit = 1), and set the REQ bit to 1
* Check the ready bit until the status = 1 * Write through the FIFO pointer register and take down
TX bit = 0), and set the REQ bit to 1.
* Check the ready bit until the status = 1 * Read through the FIFO pointer register, and record
the data number that has been written
* Repeat steps 2 and 3 until writing is complete or the
the data number that has been read.
* Repeat steps 2 and 3 until the ready bit becomes 0
ready bit becomes 0 which indicates that the FIFO no longer allows any data writing. * Set MISC TX bit = 0
* Clear the REQ bit to 0. Complete writing.
which indicates the end of the FIFO data reading.
* Set MISC TX bit = 1 * Clear the REQ bit to 0. Complete reading.
User reads the data through the FIFO pointer register, user has to record the number of bytes to be read. The
User writes the data through the FIFO pointer register, user has to record the number of bytes that have been written. The HT82J97E allows a maximum of 8 bytes of data in each packet.
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There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 can be read or not Check whether FIFO1 can be written to or not Write 0-sized packet sequence to FIFO 0 MISC Setting Flow and Status 00H(R)01H(R)delay of 2ms, check 41H(R)read* from FIFO0 register and check if not ready (01H)(R)03H(R)02H 0AH(R)0BH(R)delay of 2ms, check 4BH(R)write* to FIFO1 register and check if not ready (0BH)(R)09H(R)08H 00H(R)01H(R)delay of 2ms, check 41H (if ready) or 01H (if not ready)(R)00H 0AH(R)0BH(R)delay of 2ms, check 4BH (if ready) or 0BH (if not ready)(R)0AH 02H(R)03H(R)delay of 2ms, check 43H(R)01H(R)00H
Note: *: There are 2ms gap existing between 2 reading actions or between 2 writing actions Register Name FIFO 0 FIFO 1 R/W R/W R/W Register Address 01001000B 01001001B Bit7~Bit0 Data7~Data0 Data7~Data0
FIFO Register Address Table USB Active Pipe Timing The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work, the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown in the signal, ACT_PIPE as well. The timing is illustrated in the Figure below.
A C T _ P IP E
U S B _ IN T
L a s t A c te d P ip e
USB Active Pipe Timing
Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82J97E will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82J97E should jump to the suspend state to meet the 500mA USB suspend current spec. In order to meet the 500mA suspend current, the programmer should disable the USB clock by clearing the USBCKEN (bit3 of the SCC) to 0. The suspend current is 400mA. The user can also further decrease the suspend current to 250mA by setting the SUSP2 (bit4 of the SCC). But if the SUSP2 is set, the user has to make sure not to enable the LVR OPT option, otherwise the HT82J97E will be reset. When the resume signal is sent out by the host, the HT82J97E will wake-up the MCU by USB interrupt and
the Resume line (bit 3 of the USC) is set. In order to make the HT82J97E function properly, the programmer must set the USBCKEN (bit 3 of the SCC) to 1 and clear the SUSP2 (bit4 of the SCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of the USC) is going to 0. So when the MCU is detecting the Suspend line (bit0 of the USC), the Resume line should be remembered and taken into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered. The following is the timing diagram:
SUSPEND U S B R e s u m e S ig n a l
U S B _ IN T
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The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from the HT82J97E, it will send a Resume signal to the device. The timing is as follows:
SUSPEND M in . 1 U S B C L K RMW K
M in .2 .5 m s
If SPS2=0, and SUSB=1, the HT82J97E is defined as a USB interface. Both the USBD- and USBD+ are driven by the USB SIE of the HT82J97E. User only writes or reads the USB data through the corresponding FIFO. Both SPS2 and SUSB default is 0. To Configure the ADC Block The HT82J97E has built-in an 8-bit A/D converter with 6 channels (PB0~PB5). In order to make the A/D converter more flexible, there are two modes: External Reference voltage and Internal Reference voltage. It can be easily configured by setting the ADREF (bit 6 of the USR). For External Reference voltage, the reference voltage of the A/D converter comes from an external PB6/VRL and PB7/VRH pins. Otherwise, the reference voltage is coming from the VDD and VSS of the MCU. PB0~PB5 is the 6-channel input of the A/D converter, it is easy to define which channel is converting by configuring ACS2~ACS0 (bit 2~0 of the ADSC). Also there are four converter clock sources to be selected by setting ADCS1 (bit 4 of the ADSC), ADCS0 ( bit 3 of the ADSC). Once the ADON (bit 6 of the ADSC) is set, it sends the start pulse through START (bit 5 of ADSC). The A/D converter will be in operation. There are EOCB (bit 7 of the ADSC) to indicate whether the A/D converter is busy or not. The EOCB is cleared when the conversion is completed. User can read the converter data by reading the register ADR. In order to meet 500mA suspend current spec., user should disable the A/D by clearing ADON before jumping to suspend mode.
U S B R e s u m e S ig n a l
U S B _ IN T
To Configure the HT82J97E as PS2 Device The HT82J97E can be defined as a USB interface or a PS2 interface by configuring the SPS2 (bit 4 of the USR) and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0, the HT82J97E is defined as PS2 interface, pin USBD- is now defined as PS2 Data pin and USBD+ is now defined as PS2 Clk pin. The user can easily read or write to the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit 5 of the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7 of the USC) respectively. The user should make sure that in order to read the data properly, the corresponding output bit must be set to 1. For example, if user wants to read the PS2 Data by reading PS2DAI, the PS2DAO should be set to 1. Otherwise it always read a 0.
The following is an A/D converter timing diagram:
T1 ADON 0 A /D START 0 C o n v e r s io n S ta r ts A /D C o n v e r s io n S ta r ts N o rm a l M o d e
D7
0
A /D
C o n v e r s io n
0 or1
A /D
C o n v e r s io n
0 or1
D0 1 EOCB P o w e r_ d o w n
A /D
C o n v e r s io n T im e
0 or1
A /D
C o n v e r s io n T im e
0 or1
A /D
C o n v e r s io n F in is h e d
A /D
C o n v e r s io n F in is h e d
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HT82J97E
To Configure PWM Block The HT82J97E has two PWM outputs (PWM1 and PWM2), which are shared with PC2, PC3 and can be easily enabled or disabled by the PWM1_EN or PWM2_EN bit of PORT_PC (16H) respectively. Also there is a one 8-bit PWMBR (PWM Base Period Register, 18H) which defines both PWM output waveform cycle period. PWM cycle period = 2561/f SYS (PWMBR+1), or 2564/fSYS(PWMBR+1) where 1/fSYS or 4/fSYS is defined by PWM_S bit of the PORT_PC (16H) For example if PWMBR = 17, 4/fSYS (T1) is selected and fSYS = 6MHz. So both output waveform cycle period is 2564/6 (17+1) = about 3072ms (0.325kHz) Now user can easily define the corresponding PWM duty by configuring the PWM1DR (for PWM1) or PWM2DR (for PWM2) duty registers PWM1 duty (high pulse) = (PWM1DR+1)/256100% PWM1 high pulse period = PWM1 dutyPWM cycle period
PW M C y c le P e r io d
PWM1 Low pulse period = PWM cycle period-high pulse period PWM2 duty (high pulse) = (PWM2DR+1)/256100% PWM2 high pulse period = PWM2 dutyPWM cycle period PWM2 Low pulse period = PWM cycle period-high pulse period For example PWMBR=17, PWM1DR=63, 4/fSYS (T1) is selected and fSYS=6MHz PWM cycle period = 2564/6(17+1) = about 3072ms (0.325kHz) PWM1 duty = (63+1)/256 = 25% PWM1 high pulse period = 25%3072ms = 768ms PWM1 low pulse period = 3072ms -768ms = 2304ms
PW M H ig h P u ls e
I/O Port Special Registers Definition
* Port-A (12H) - PA
Register
Bits 0 1 2 3
Labels PA0 PA1 PA2 PA3 PA4 PA5 PA6
Read/Write R/W R/W R/W R/W R/W R/W R/W
Option 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Functions I/O (R/W) has pull-low and pull-high ROM code option. Has falling edge wake-up ROM code option. I/O (R/W) has pull-low and pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-low and pull-high option. Has falling edge and rising edge wake-up option. I/O (R/W) has pull-low and pull-high option. Has falling edge and rising edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option, pin-shared with timer input pin.
PA (12H)
4 5 6
7
PA7
R/W
* Port-A Control (13H) - PAC
This port configure the input or output mode of Port-A
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* Port-B Control (14H) - PB
Register
Bits 0 1 2 3
Labels PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Option 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Functions I/O (R/W), has pull-high option, ADC input. I/O (R/W), has pull-high option, ADC input. I/O (R/W), has pull-low and pull-high option, ADC input. I/O (R/W), has pull-low and pull-high option, ADC input. I/O (R/W), has pull-high option, can wake-up, ADC input. I/O (R/W), has pull-high option, ADC input. I/O (R/W), has pull-high option, ADC input, VRL input for ADC external mode. I/O (R/W), has pull-high option, ADC input, VRH input for ADC external mode, has wake-up capability.
PB (14H)
4 5 6 7
* Port-B Control (15H) - PBC
This port configures the input or output mode of Port-B for I/O mode
* Port-C Control (16H) - PC
Register
Bits 0 1 2 3
Labels PC0 PC1 PC2 PC3 PC4 PC5
Read/Write R/W R/W R/W R/W 3/4 R/W
Option 3/4 3/4 3/4 3/4 3/4 PWM_S
Functions I/O (R/W), has pull-high option I/O (R/W), has pull-high option I/O (R/W), has pull-high option, can be used as PWM1 output I/O (R/W), has pull-high option, can be used as PWM2 output Reserved bit PWM base period register frequency source 0= T1 (default) 1= fSYS 1: Internal register bit, enable PWM1 output 0: Disable (default) 1: Internal register bit, enable output 0: Disable (default)
PC (16H)
4 5
6 7
PC6 PC7
R/W R/W
PWM1_EN PWM2_EN
* Port-C Control (17H) - PCC
This port is used to control whether the Port-C pin is input or output pin except PC4~PC7
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USB/PS2 Status and Control Register USC (Address 0X1A) Register Bits 0 1 2 3 USC (0X1A) 4 5 6 7 Labels PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Read/Write R W R/W R R R W W Option SUSPEND RMOT_WK Functions USB suspend mode status bit. When 1, indicates that the USB system entry is in suspend mode. USB remote wake-up signal. Default value is 0.
URST_FLAG USB bus reset event flag. Default value is 0. RESUME_O PS2_DAI PS2_CKI PS2_DAO PS2_CKO When RESUME_OUT EVENT, RESUME_O is set to 1. Default value is 0. USBD-/DATA input USBD+/CLK input Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. Default value is 1. Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. Default value is 1.
Endpoint Interrupt Status Register USR (Address 0X1B) The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (PS2 or USB) and A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and a USB interrupt will occur (If a USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0. Register Bits Labels Read/Write Option Functions When set to 1, indicates an endpoint 0 interrupt event. Must wait for the MCU to process the interrupt event and clear this bit by firmware. This bit must be 0, then the next interrupt event will be processed. Default value is 0. When set to 1, indicates an endpoint 1 interrupt event. Must wait for the MCU to process the interrupt event, then clear this bit by firmware. This bit must be 0, then the next interrupt event will be processed. Default value is 0. Reserved bit, set to 0 Reserved bit, set to 0 When set to 1, indicates that the chip is working under PS2 mode. Default value is 0. When set to 1, indicates that the chip is working under USB mode. Default value is 0. When set to 0, indicates the reference voltage of the 8-bit ADC from the external input pin. When set to 1, indicates that the reference voltage is from the internal power line. Default value is 1. This flag is used to show that the MCU is in USB mode (Bit=1). This bit is R/W by FW and will be cleared to zero after power-on reset. The default is 0.
0
PEC0
R/W
EP0IF
1
PEC1
R/W
EP1IF
2 USR (0X1B) 3 4 5
PEC2 PEC3 PEC4 PEC5
R/W R/W R/W R/W
3/4 3/4 SELPS2 SELUSB
6
PEC6
R/W
VRSEL
7
PEC7
R/W
USB_flag
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Clock Control Register SCC (Address 0X1C) There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2) and system clock selection (SCLKSEL). Register Bits 2~0 3 4 5 Labels PF2~PF0 PF3 PF4 PF5 Read/Write R/W R/W R/W R/W Option 3/4 USBCKEN SUSPEND2 3/4 Reserved USB clock control bit. When set to 1, indicates a USBCK ON, else USBCK OFF. Default value is 0. When set to 1, enables a 7.5kW resistor connected to D-pin to 5V VDD. Default value is 0. Reserved System clock 6MHz or 12MHz option, when working on external oscillator mode. Default value is 0. 0: Operating at external 12MHz mode 1: Operating at external 6MHz mode Default value is 0. This flag is used to show that the MCU is in PS2 mode (Bit=1). This bit is R/W by FW and will be cleared to zero after power-on reset. The default is 0. Functions
SCC (0X1C)
6
PF6
R/W
SCLKSEL
7
PF7
R/W
PS2_flag
ADC Status and Control Register ADC (Address 0X1D) The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal power supplies of the MCU (VDD and VSS). The VRL and VRH are used to set the minimal and maximal boundaries of the full-scale range of the A/D converter. If an analog input, VRL or VRH is not used for A/D conversion, it can also be used as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the configurations and A/D clock sources of the A/D converter and controls the operation of the A/D converter. Register Bits Labels Read/Write Option Functions These four bits selects one of the eight ADC channels for conversion. Channels 0 to 5 correspond to inputs AD0~AD5 on port pins PB0-PB5 respectively. Channels 6 and 7 are the ADC reference inputs VRH and VRL, on port pins PB6 and PB7 respectively. 000: AD0 (PB0); 001: AD1 (PB1) 010: AD2 (PB2); 011: AD3 (PB3) 100: AD4 (PB4); 101: AD5 (PB5) 110: AD6 or VRL (PB6); 111: AD7 or VRH (PB7) Default value is 000B. Selecting ADC operating clock. 00: 6MHz (Default clock) 01: 3MHz 10: 1.5MHz 11: 0.75MHz Start of ADC conversion. High active. Default value is 0 Enable pin. ADON=1, Enable ADC block. Default value is 0. End of conversion. This read-only status bit is cleared when a conversion is completed, indicating that the ADC Data Register contains a valid result.
2~0 PFC2~PFC0
R/W
SEL_CH
ADC (0X1D)
4~3 PFC4~PFC3
R/W
SEL_CLK
5 6
PFC5 PFC6
R/W R/W
START ADON
7
PFC7
R/W
EOCB
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HT82J97E
ADC High-byte Data Register ADCR (Address 0X1E) Register Bits ADCR (0X1E) 7~0 Labels PG7~PG0 Read/Write R Option ADCDR Functions The ADCDR stores the result of a valid ADC conversion bit7~bit0.
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F) Register Bits TBHP (0X1F) 2~0 Labels PGC2~PG0 Read/Write R Option 3/4 Functions Store current table read bit10~bit8 data
PWM Base Period Register PWMBR (Address 0X18) This register is used to define the base period of the PWM cycle period. The period is defined according to the following equation: Base period = (4/fSYS)(PWMBR+1) or (1/fSYS) (PWMBR+1) Where 4/fSYS or 1/fSYS is defined by PWM_S bit of PORT_PC Where PWMBR = 1~255, PWMBR=0 is not available PWM cycle period = 256Base period Base period equals to 1/256 duty cycle. Register Bits PWMBR 7~0 (0X18) Labels PD7~PD0 Read/Write R Option 3/4 Functions Used to define the base period of the PWM Range =2~256Base Period Where PWMBR=1~255, PWMBR=0 is not available
PWM Duty Register PWM1DR (Address 0XCH) and PWM2DR (Address 0XDH) This register is used to define the duty of the PWM1 output (PC2) or PWM2 output (PC3) respectively. Both PWM cycle frequency is defined according to the following equation: Register PWM1DR (0XCH) PWM2DR (0XDH) Bits 7~0 Read/Write R/W Option 3/4 Functions Used to define the PWM duty
PWM1 duty = (PWM1DR+1)/PWM cycle100% period Where PWM1DR= 0~255 If the PWM function is enabled by setting the corresponding bit (PWM1_EN or PWM2_EN of Port C), the PWM output (PC2 or PC3) pins always output the PWM signal whether the corresponding control register bit (PCC2 or PCC3 ) is defined as in input or output mode. OTP Options No. 1 2 3 4 5 6 7 8 9 10 WDT clock source: RC (system/4) (default: T1) WDT clock source: enable/disable for normal mode (default: disable) PA0~PA7 ,PB4, PB7 wake-up by bit (PA2, PA3 both wake-up by falling or rising edge) (default: non wake-up) PA0~PA7 pull-high by bit (default: Pull-high) PC0~3,PB pull-high by nibble (default: Pull-high) 2.7 V (error 0.3V) LVR enable/disable (default: enable) PA0~PA3, PB2, PB3 Pull-low by bit (default: non pull-low 30kW) CLR WDT, 1 or 2 instructions TBHP enable/disable (default: disable) PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Option
The LVR voltage is define as 2.7V0.3V and default is enable.
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HT82J97E
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
VDD USBUSB+ VSS 0 .1 m F
5W
*
10mF
33W
*
100kW 0 .1 m F 22pF **
*
VDD
PA0~PA7 PB0~PB7 PC0~PC3
X1
OSC1
V33O
OSC2
1 .5 k W
0 .1 m F
5W
*
0 .1 m F
22pF 10kW ** 0 .1 m F
47pF*
*
*
RES
U S B D -/D A T A 47pF*
33W
* *
*
47pF 33W
VSS
U S B D + /C L K
H T82J97E
*
47pF
Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only.
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HT82J97E
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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HT82J97E
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC[M](5) Read ROM code (locate by TBLPand TBHP) to data memory and TBLH TABRDC [m](6) Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF 2(1) 2(1) 2(1) None None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. : ROM code TBHP option is enabled : ROM code TBHP option is disabled
(5) (6)
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HT82J97E
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Rev. 1.30
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HT82J97E
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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HT82J97E
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. PC PC+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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HT82J97E
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
Rev. 1.30
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HT82J97E
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 Rev. 1.30 PDF 3/4 OV 3/4 36 Z 3/4 AC 3/4 C O May 10, 2004
HT82J97E
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
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HT82J97E
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
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HT82J97E
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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HT82J97E
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code TBHP is enabled) The low byte of ROM code addressed by the table pointers (TBLPand TBHP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory (ROM code TBHP is disabled) The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
40
May 10, 2004
HT82J97E
TABRDL [m] Description Operation Affected flag(s) TO 3/4 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.30
41
May 10, 2004
HT82J97E
Package Information
20-pin SOP (300mil) Outline Dimensions
20
A
11
B
1
C C'
10
G H
D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 490 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 510 104 3/4 3/4 38 12 10
Rev. 1.30
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May 10, 2004
HT82J97E
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.30
43
May 10, 2004
HT82J97E
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 20W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
Rev. 1.30
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May 10, 2004
HT82J97E
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
K0 A0
SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0+0.3 -0.1 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.80.1 13.30.1 3.20.1 0.30.05 21.3
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.30
45
May 10, 2004
HT82J97E
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
46
May 10, 2004

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